1. Field of the Invention
In general, the present invention relates to a method for manufacturing electric charge transferring devices. In particular, the present invention relates to a method for manufacturing electric charge transferring devices which method allows transfer gate electrodes to be formed into a single-layer structure.
2. Description of the Related Art
FIGS. 4A to 4C are diagrams relevant to a typical conventional electric charge transferring device. FIG. 4A is a cross-sectional diagram and FIG. 4B is a potential diagram used for explaining transferring operations. FIG. 4C is a pulse diagram showing driving clock pulses for the transferring operations. A manufacturing method of this typical electric charge transferring device is adopted for manufacturing electric charge transferring devices of a two-phase transferring system, many of which devices are used as horizontal registers employed in a CCD type solid-state video photographing apparatus.
Reference numeral 1 shown in the figures is a P-type semiconductor substrate whereas reference numeral 2 is an N-channel layer formed on the surface of the semiconductor substrate 1. Reference numerals 3 are N-type transfer portions which are laid out on the surface of the N-channel layer 2 in the transfer direction at locations separated from each other by a predetermined distance. The N-type transfer portions 3 are formed by selectively doping the N-channel layer 2 with P-type impurities. Reference numerals 4 are each a region of the N-channel layer 2 on the transfer destination side of the transfer portion 3 which region forms a storage portion. As a matter of fact, the storage regions 4 are portions of the N-channel layer 2 which are not doped with the P-type impurities described above. In other words, the storage regions 4 can be said to be the N-channel layer 2 as it is.
Reference numeral 5 is a gate insulating layer formed on the surface of the semiconductor. Reference numerals 6s, 6t, 6s, 6t, . . . etc. are transfer gate electrodes made of polycrystal silicon. The transfer gate electrodes 6s, 6s, . . . are made of a first silicon layer located on the storage portions 4, 4, . . . The transfer gate electrodes 6t, 6t . . . are, on the other hand, made of a second silicon layer located on the transfer portions 3, 3, . . . It should be noted that reference numeral 7 is an insulating layer whereas reference numeral 8 is an interlayer insulating layer.
FIG. 3C shows two-phase driving pulses .phi.1 and .phi.2. The principle of the transfer operation is explained below by paying attention to, for example, a pair of transfer gate electrodes 6t and 6s to which the driving pulse .phi.1 is applied.
In other words, the driving pulse .phi.1 is applied to the transfer gate electrode 6t on one of the transfer portions 3 and the transfer gate electrode 6s forming a pair in conjunction with the transfer gate electrode 6t on the storage portion 4 on the transfer destination side of the transfer portion 3. By selective ion injection of P-type impurities into the transfer portion 3, the N-type impurity concentration of the transfer portion 3 can be made lower than that of the storage portion 4. Accordingly, a difference in potential of the order of 2 to 3 V between the transfer portion 3 and the storage portion 4 is developed even if the same voltage is applied. As a result, the storage portion 4 has a deeper potential. For this reason, electric charge is probably transferred through the transfer portion 3 and collected at the storage portion 4.
At a point of time t=t1, one of the driving clock pulses .phi.1 is raised to a high-level voltage (of 5 V in the case of this example) while the other driving clock pulse .phi.2 goes down to a low-level voltage (of 0 V in this example). At that time, the regions below the transfer gate electrodes 6s, 6s,--made from the first silicon layer, that is, the transfer portions 4, 4,--enter a state of signal charge being accumulated.
Later on, the time lapses, arriving at a point of time t=t3 after passing a point of time t=t2. With this lapse of time, the phases of the driving clock pulses .phi.1 and .phi.2 are inverted and, as shown in FIG. 4B, the signal charge is transferred in the direction to the right shown in the figure.
By the way, one of reasons why the transfer gate electrodes 6s, 6t, 6s, 6t, . . . are built into a multi-layer structure as shown in FIG. 4A is to make any two adjacent transfer gate electrodes 6s and 6t overlap each other. In this way, no potential pocket is made below a space between two adjacent gate insulating layers. In this example, the multi-layer structure comprises two layers. It should be noted, however, that the structure may comprise three layers. That is to say, if the transfer gate electrodes 6s, 6t, 6s, 6t, . . . are formed from a single polycrystal silicon layer by means of the conventional technology, the gap between two adjacent transfer gate electrodes 6s and 6t inevitably increases as shown in FIG. 5A. In this case, a region on which the effect of the magnetic field generated by the transfer electrodes decreases is developed beneath a space between the two adjacent transfer gate electrodes 6s and 6t. As a result, a potential pocket like the one shown in FIG. 5B is developed between any two adjacent transfer gate electrodes. Since the potential pocket can become a place for electric charge to accumulate, some electric charge is left untransferred.
For this reason, according to the conventional technology, the transfer gate electrodes . . . are built into a two-layer structure so as to make any two adjacent transfer gate electrodes overlap each other. FIGS. 6A and 6B are diagrams used for explaining why the transfer gate electrodes are formed into a two-layer structure. FIG. 6A is a cross-sectional diagram whereas FIG. 6B is a potential diagram.
That is to say, by forming a two-layer structure, any two adjacent transfer gate electrodes can be built to overlap each other. In such a structure, the reduction in effect of the electric field on the channel between two adjacent transfer gate electrodes is decreased. In its turn, the potential pocket decreases in size as shown in FIG. 6B. As a result, the amount of signal charge left untransferred due to the potential pocket also decreases as well.
FIGS. 7A to 7G are cross-sectional diagrams showing an order of processes of a method for forming transfer gate electrodes into a multi-layer structure.
(A) As shown in FIG. 7A, after a gate insulating layer 7 is formed on the surface of a channel 2, a first polycrystal silicon layer 6a is formed on the gate insulating layer 7. PA1 (B) Next, as shown in FIG. 7B, resist layers 9 are formed selectively on the first polycrystal silicon layer 6a. The resist layers 9 are formed so as to cover storage portions which are not shown in FIG. 7. PA1 (C) Next, transfer gate electrodes 6s, 6s, . . . are formed by etching the polycrystal silicon layer 6a using typically the RIE technique with the resist layers 9 used as a mask. Later on, the polycrystal silicon layer 6a is removed. A state with the polycrystal silicon layer 6a removed is shown in FIG. 7C. It should be noted that the surfaces of exposed portions on the gate insulating layer 7 are slightly etched by the RIE technique. (D) Next, as shown in FIG. 7D, interlayer insulating layers 8 are formed by thermally oxidizing the surface of the polycrystal silicon layer 6a. It should be noted that, at that time, a silicon oxide layer grows on the gate insulating layer 7 so that the gate insulating layer 7, which once became thin in the previous process (C), returns approximately to a predetermined thickness. PA1 (E) Next, as shown in FIG. 7E, a second polycrystal silicon layer 6b is formed by means of the CVD technique. PA1 (F) Next, as shown in FIG. 7F, resist layers 10 are formed selectively on the polycrystal silicon layer 6b. To put it in more concrete terms, the resist layers 10 are formed so as to cover regions at which transfer gate electrodes 6t for driving the transfer portions, not shown in FIG. 7, are to be formed. PA1 (C) Next, transfer gate electrodes 6t, 6t, . . . are formed by etching the polycrystal silicon layer 6b using typically the RIE technique with the resist layers 10 used as a mask. Later on, the resist layers 10 are removed. A state with the resist layers 10 removed is shown in FIG. 7G. PA1 At the end of the process (G), the creation of the transfer gate electrodes into a multi-layer structure is completed. PA1 forming a polycrystal silicon layer to serve as a material for forming the transfer gate electrodes on a gate insulating layer; PA1 forming a mask layer on the polycrystal silicon layer with a pattern having openings on portions exposed to boundaries between any two adjacent transfer gate electrodes; PA1 etching the polycrystal silicon layer with the mask layer used as a mask; and PA1 oxidizing the surface of the polycrystal silicon layer. PA1 forming a polycrystal silicon layer to serve as a material for forming the transfer gate electrodes on a gate insulating layer; PA1 forming an oxidation-proof layer on the polycrystal silicon layer; PA1 forming a mask layer on the oxidation-proof layer with a pattern having openings on portions exposed to boundaries between any two adjacent transfer gate electrodes; PA1 etching the oxidation-proof layer with the mask layer used as a mask; and PA1 oxidizing the surface of the polycrystal silicon layer through openings formed on the oxidation-proof layer at the etching step. PA1 forming a mask layer on the polycrystal silicon layer with a pattern having openings on portions exposed to boundaries between any two adjacent transfer gate electrodes; PA1 etching the polycrystal silicon layer with the mask layer used as a mask; and PA1 oxidizing the surface of the polycrystal silicon layer, PA1 allowing any two adjacent transfer gate electrodes to be insulated from each other by a silicon oxide layer formed at the oxidizing step. PA1 forming an oxidation-proof layer on the surface of a polycrystal silicon layer after the step of forming the polycrystal silicon layer and prior to the step of forming a mask layer; and PA1 etching the oxidation-proof layer with the mask layer used as a mask, allowing openings to be formed on the oxidation-proof layer above the gap between any two adjacent transfer gate electrodes. Then, the surface of the polycrystal silicon layer is oxidized through the openings formed on the oxidation-proof layer at the etching step, allowing any two adjacent transfer gate electrodes to be insulated from each other by a silicon oxide layer formed during the oxidization.
Problems to be Solved by the Invention
By the way, according to the conventional method of manufacturing electric charge transferring devices, a multicrystal silicon layer is first formed and transfer gate electrodes are then formed by patterning in an etching process which uses resist layers selectively formed as a mask. It is necessary to repeat these process a plurality of times. On the top of that, a process to forme an interlayer insulating layer by thermal oxidation on the surfaces of the transfer gate electrodes made from the polycrystal silicon layer is also required, giving rise to problems that the number of manufacturing processes increases and the manufacturing cost also becomes higher as well.
In addition, as the number of manufacturing processes increases, the yield is inevitably decreased. The decreased yield also becomes one of the causes of the rising manufacturing cost.
Furthermore, the above conventional method of manufacturing electric charge transferring devices also has a problem that there is a difference in magnitude between the thickness T1 of the gate insulating layer 7 beneath the transfer gate electrode 6s made from the first polycrystal silicon layer and the thickness T2 of the gate insulating layer 7 beneath the transfer gate electrode 6t made from the second polycrystal silicon layer. This problem is not desirable because it gives rise to a trouble in that there is a difference in electric field effect caused by the same gate voltage between the storage and transfer portions. This problem is caused by the following processes. After the gate insulating layer 7 has been formed, the thickness of the layer of the exposed portion is decreased by the etching carried out at the process (C). Later on, at the next process (D), the thermal oxidation is carried out, causing a silicon oxide layer to grow at the exposed portion. The thickness of the layer at the exposed portion thus increases. However, it is extremely difficult to make the decrease in layer thickness resulting from the RIE process equal to the increase in layer thickness gained during the thermal oxidation.